In an array of memory cells of a floating gate type EEPROM with a NAND structure, as represented by an equivalent circuit thereof in FIG. 1, each memory cell 11 is formed by a single N-channel transistor. Eight memory cells 11 corresponding to a 1 byte, or 8-bit memory cell, are series-connected to each other in such a manner that transistors for forming the mutually adjoining memory cells 11 commonly own the diffusion layer. One end of eight memory cells 11 series-connected to each other is connected to a source of a first selecting transistor 12, and a drain of the first selecting transistor 12 is connected to a bit line 13. The other end of eight memory cells 11 series-connected to each other is connected to a drain of a second selecting transistor 14, and a source of the second selecting transistor 14 is connected to a ground line 15. A control gate of the N-channel transistor for forming the memory cell 11 is connected to a word line 16, whereas control gates of N-channel transistors constituting the eight memory cells 11 series-connected to each other are connected to the different word lines 16, respectively. One ends of the word lines 16 are connected to an X-decoder 17. The other ends of the word lines 16 are connected to high voltage transistors 18. These high voltage transistors are connected to the corresponding word lines 16, respectively. One end of the bit line 13 is connected to a Y-decoder 21, and the other end of the bit line 13 is connected to a sense amplifier 22. In such a constructed EEPROM, the first selecting transistor 12 and the second selecting transistor 14 are also constructed of N-channel transistors.
The N-channel transistor for constituting the memory cell 11 is fabricated as follows. As illustrated in FIG. 2B, a P-type well 24 is formed within an N-type semiconductor substrate 23, and diffusion layers 25 functioning as the source and the drain are formed within the P-type well 24. A floating gate electrode 32 is formed via a gate insulating film 31 on a channel region 26 between two diffusion layers 25. The word line 16 functioning also as a control gate electrode is formed via a gate insulating film 33 on the floating gate electrode 32. An initial value of a threshold voltage of the N-channel transistor for constituting the memory cell 11, namely a threshold voltage under non-writing state is set to a negative value.
In the EEPROM with such a structure, to write data into, for instance, the memory cell 11 ( referred to as "selective memory cell Mi,j" hereinafter) shown in a central left portion of FIG. 2A, the potentials at the word line 16 (will be referred to as "selective word line Xi" hereinafter) connected to the selective memory cell Mi,j and the gate electrodes of the first selecting transistors 12 are set to 20 V (see FIG. 2A) under such a condition that the potentials at the semiconductor substrate 23 and the P-type well 24 are set to 0 V (see FIG. 2B). At this time, the potentials at the word lines 16 connected to the memory cells 11 (referred to as "non-selective memory cells" hereinafter) other than the selective memory cell Mi,j are set to 7 V, and the potentials at the gate electrodes of the second selecting transistors 14 are set to 0 V. The potential at the bit line 13 (referred to a "selective bit line Yi" hereinafter) related to the selective memory cell Mi,j is set to 0 V by way of the Y-decoder 21, and the potentials at other bit lines 13 (referred to as "non-selective bit lines" hereinafter) are set to 7 V by the Y-decoder 21. Under such a condition, since all of the N-channel transistors for forming the memory cells connected between the first selecting transistor 12 and the selective memory cell Mi,j are brought into the conductive conditions, the 0 V-potentional at the selective bit line Yi is transferred to the drain of the N-channel transistor for forming the selective memory cell Mi,j. As a result, since the potential at the channel region 26 of the N-channel transistor for forming the selective memory cell Mi,j is also set to 0 V, a potential difference between this channel region 26 and the selective word line Xi becomes 20 V, the Fowler-Nordheim current flows through the gate insulating film 31, and electrons are injected into the floating gate 32 of the N-channel transistor for forming the selective memory cell Mi,j. As a consequence, the threshold voltage of the N-channel transistor for forming the selective memory cell Mi,j is changed from a negative value to a positive value (normally, 0 to 3.5 V).
It should be noted that the potential at the selective word line Xi becomes 20 V, to which the non-selective memory cell Mi,j+1 located at the right side of the selective memory cell Mi,j shown in FIG. 2A is connected. However, since the potential at the non-selective bit line Yj+1 related to the non-selective memory cell Mi,j+1 becomes 7 V, and also the potential at the channel region 26 of the N-channel transistor for forming the non-selective memory cell Mi,j+1 becomes 7 V similarly, a potential difference between this channel region 26 and the selective word line Xi is only 13 V. As a result, since no Fowler-Nordheim current flows through the gate insulting film 31 of the N-channel transistor for forming the non-selective memory cell Mi,j+1, no erroneous writing operation is carried out. A potential at a word line (referred to as "non-selective word line Xi+1" hereinafter), to which the non-selective memory cell Mi+1,j located at the lower side of the selective memory cell Mi,j shown in FIG. 2A is connected, becomes 7 V. However, also under this condition, a potential difference between the non-selective word line Xi+1 and the channel region 26 of the N-channel transistor for forming the non-selective memory cell Mi+1,j is only 7 V. As a consequence, no Fowler-Nordheim current flows through the gate insulating film 31 of this N-channel transistor, and thus no erroneous writing operation is performed.
In the reading operation of the data from the selective memory cell Mi,j, as illustrated in FIG. 3, the potentials at the gate electrodes of the first selecting transistors 12, the gate electrodes of the second selecting transistors 14, and the word lines other than the selective word line Xi are set to 5 V, so that the first selecting transistors 12, the second selecting transistors 14, and the non-selective memory cells are brought into the conductive conditions. Further, the potential at the selective word line Xi is set to 0 V and the potential at the selective bit line Yi is set to 5 V. The non-selective bit lines such as the non-selective bit line Yi+1 are brought into open conditions. At this time, if the data has been written into the selective memory cell Mi,j, and the threshold voltage of the N-channel transistor for forming the selective memory cell Mi,j is positive, then this N-channel transistor does not become conductive, but a voltage of 5 V is applied to the sense amplifier 22. As a result, data of "0" is outputted from the sense amplifier 22. On the other hand, if no data has been written into the selective memory cell Mi,j and the threshold voltage of the N-channel transistor for forming the selective memory cell Mi,j is negative, then this N-channel transistor becomes conductive, and the voltage of 0 V is applied to the sense amplifier 22. As a result, data of "1" is outputted from the sense amplifier 22.
In case that the data written into the selective memory cell Mi,j is erased, the potential at the P-type well 24 is set to 12 V, and also the potential at the selective word line Xi is set to 0 V. As a consequence, the electrons present in the floating gate electrode 32 of the N-channel transistor for forming the selective memory cell Mi,j is ejected as a Fowler-Nordheim current into the P-type well 24. It should be noted that in this case, since the electrons present in the floating gate electrode 32 are similarly ejected into the P-type well 24 in other memory cells (non-selective memory cell Mi,j+1 etc.) to which the selective word line Xi is connected, the data erasing operation is carried out in unit of the word line 16.
However, in the above-described prior art, during the data writing operation, the threshold voltages of the memory cells 11 under the non-writing state set to the negative values are brought into the positive values. On the other hand, during the data reading operation of this prior art, the potentials at the word lines to which the non-selective memory cells are connected are brought into 5 V, so that the non-selective memory cells are brought into the conductive conditions. As a result, if the threshold voltages of the memory cells 11 would not be selected to be lower than, or equal to 3.5 V even under the data writing state, then the resultant current during the conductive condition of the memory cells would become low, and the accessing speed to the selective memory cell Mi,j would be lowered. The value of the threshold voltage of the memory cell 11 under such a condition that the data has been written therein will depend on the amount of the injected electrons, and large fluctuation may occur in the amount of the injected electrons. If an excessive data writing operation is performed, an excessive amount of electrons is injected. This may cause the threshold voltage of the memory cell 11, to which the data has been written, to be higher than, or equal to 3.5 V. As a consequence, the accessing speed to the selective memory cell Mi,j is not always fast in the above-explained prior art.